The objective of the hArtes tool-chain is to simplify the end-to-end development of embedded products, from the definition of the algorithms to the synthesis on silicon or on existing hardware, which may include heterogeneous and reconfigurable components.

The toolchain is composed of a set of tools, out of the hArtes tool-boxes, which may be linked together in a coherent workflow, where each tool is perfoming a vital role in the design process.

The hArtes Eclipse framework is the development environment which is integrating hArtes tools in a coherent workspace, which may be specialized to address specific development exigencies.

The hArtes tools are grouped in the following three toolboxes:

1) Algorithm Exploration and Translation Tool-Box;

2) Design Space Exploration (DSE) Tool-Box;

3) System Synthesis (SysSyn) Tool-Box.

Before the VHDL outcome of the synthesis enters the silicon design process, the result is emulated through the SoC Emulation Platform.

The input of this tool-chain is a high level application algorithm, described in one of several supported formats and languages, such as, graphical description, SciLab code or handcrafted C. The internal representation of the application algorithms is C code, annotated with pragmas by the tools in the toolchain.

 The objectives of each hArtes Tool-Box can be summarized as follows:

• The Algorithm exploration and translation Tool-Box provides tools with two basic functionalities. They assist the designers to instrument and possibly improve the input algorithm at the highest level of abstraction. Also, they translate the input algorithms, described in different formats and languages (e.g., SciLab or graphical entry through Nu-Tech), into a unified internal description in the C language.
• The Design space exploration ToolBox provides an optimal hardware/software partitioning of the input algorithm for each reconfigurable heterogeneous system considered. A set of profilers and cost estimators employ specific metrics to evaluate a particular mapping of a candidate application on the particular reconfigurable heterogeneous system with respect to performance, hardware complexity, etc. The input of the DSE ToolBox is the C description of the application algorithm, annotated with specification directives from the algorithm exploration and translation ToolBox, and models of the reconfigurable heterogeneous system platform. The DSE output is an optimized partitioning of the application algorithm for the considered reconfigurable heterogeneous system.
• The System synthesis ToolBox processes the optimized partitioning of the application algorithm provided by the DSE ToolBox as its input. The output comprises all generated files, required to map the application algorithm on the components of the considered reconfigurable heterogeneous system with respect to its partitioning, i.e., program executables, configuration bitstreams, memory images, etc.

 The hArtes workspace which has been created for a design process may include all the above mentioned hArtes tools, or part of them, depending on the requirements of the embedded application and on the objective of the design, which could be the integration of the application using existing hardware as well as  the development of a new SoC component.